1. Technical Field
The present disclosure relates to a digital control device of a switching power supply.
2. Description of the Related Art
It is generally known to use devices for actively correcting the power factor (PFC) of switching power supplies used in common electronic apparatuses such as computers, televisions, monitors, etc., and for supplying power to fluorescent lamps, i.e., switching pre-regulator stages which must absorb a current from the power line, said current is quasi-sinusoidal and in phase with the supply voltage. A switching power supply of the current type thus comprises a PFC and a DC-DC converter connected to the PFC output.
A typical switching power supply comprises a DC-DC converter and an input stage connected to the power distribution line which comprises a full-wave diode rectifier bridge and a capacitor connected downstream so as to produce a non-regulated direct voltage from the sinusoidal alternating supply voltage. The capacitor has a great enough capacitance for a relatively small ripple being present at its terminals as compared to a direct level. Therefore the rectifier diodes of the bridge will only conduct over a short portion of each half cycle of the supply voltage, as the instantaneous value thereof is less than the voltage of the capacitor over most of the cycle. The result is the current absorbed by the power line consists of a series of short impulses the amplitude of which is 5-10 times the resulting average value.
This has significant consequences: the current absorbed from the power line has peak and rms (root-mean-square) values much higher than the case of sinusoidal current absorption, the supply voltage is distorted due to the almost simultaneous impulse absorption of all utilities connected to the power line, the current in the neutral conductor in the case of three-phase systems is highly increased and there is low use of the energy potentials of the power system. In fact, the waveform of impulse current includes many odd harmonics, which although they do not contribute to the power provided to the load, they contribute to increasing the rms current absorbed by the power line and therefore to increasing the energy dissipation.
In quantitative terms, this may all be expressed both in terms of Power Factor (PF), intended as ratio of the real power (the one the power supply sends to the load plus the one dissipated therein in the form of heat) to the apparent power (the product of the rms voltage by the rms current absorbed), and in terms of Total Harmonic Distortion (THD), generally intended as percentage ratio of the energy associated with all larger harmonics to the one associated with the fundamental harmonic. Typically, a power supply with capacitance filter has a PF between 0.4 and 0.6 and a THD higher than 100%.
A PFC arranged between the rectifier bridge and the input of the DC-DC converter allows a current quasi sinusoidal and phased with the voltage, to be absorbed from the network, thus making the PF close to 1 and decreasing the THD.
FIG. 1 schematically shows a PFC pre-regulator stage comprising a boost converter 20 and a control device 1. The PWM control device has a variable frequency, also called “Transition Mode” (TM) as the device works on the borderline between the continuous (CCM) and discontinuous (DCM) modes of conducting current through the inductor; in particular, device 1 is of the constant Ton type. According to this method, the turn-on period of the power transistor is used as a control variable and, during each cycle of the supply voltage, it is kept constant at the value required to obtain the regulation of the voltage output from the converter 20 by means of a feedback control loop. The boost converter 20 comprises a full-wave diode rectifier bridge 2 having an input supply voltage Vac, a capacitor C1 (which serves as a high frequency filter) having a terminal connected to the diode bridge 2 and another terminal connected to ground GND and on which a voltage Vin exists, an inductance L connected to a terminal of the capacitor C1, a MOS power transistor M having its drain terminal connected to a terminal of the inductance L downstream of the latter and having its source terminal connected to ground GND, a diode D having its anode connected to the common terminal of the inductance L and the transistor M, and its cathode connected to a capacitor Co having another terminal connected to ground GND. The boost converter 20 generates an output direct voltage Vout across the capacitor Co which is higher than the maximum peak supply voltage, typically 400 V for systems powered by means of European power line or universal power line. Such a voltage Vout will be the input voltage of the DC-DC converter connected to the PFC.
The control device 1 should keep the output direct voltage Vout at a constant value by means of a feedback control action. The control device 1 comprises an operational error amplifier 3 adapted to compare part of the output voltage Vout, i.e., the voltage Vr given by Vr=R2×Vout/(R2+R1) (where the resistances R1 and R2 are connected in series to each other and the series is in parallel to the capacitor Co) with a reference voltage Vref, e.g., of the value of 2.5 V, and generates an output error signal Se across a capacitor Ce connected between the output of amplifier 3 and ground GND.
The error signal Se is sent to the inverting input of a comparator PWM 5 while the signal Srs exists at the non-inverting input; the signal Srs is a voltage ramp across a capacitor Cc powered by a current generator Ic in the time periods whenever the switch T1 is open, which coincide with those when M is on as precisely the duration Ton of the turn-on of M is to be controlled. If signals Srs and Se are equal, the comparator 5 sends a signal to a control block 6 adapted to control the transistor M and which, in this case, turns it off. Block 6 comprises a zero current detecting block 7 having at the input the signal Saux deriving from the inductor Laux coupled with the inductor L; the signal Saux is representative of the demagnetization of the core of the transformer formed by the inductances L and Laux. Block 7 is capable of sending an impulse signal to a OR gate 8, the other input of which is connected to a starter 10 adapted to send a signal to the OR gate 8 at the initial instant of time. The output signal S of the OR gate 8 is the set input S of a set-reset flip-flop 11 having another input R which is the signal at the output from the comparator 5, and having an output signal Q and an output signal Q* which is the negated signal Q. The signal Q is sent to the input of a driver 12 which controls the turn-on or turn-off of the transistor M and therefore the duration of the turn-on time period Ton and the turn-off time period Toff in each switching cycle Tsw while the signal Q* controls the closing and opening of switch T1.
FIG. 2 shows the time diagrams of some signals involved in the circuit in FIG. 1, i.e., the voltage between the gate and source terminals of transistor M Vgs, the voltage between the drain and source terminals of transistor M Vds and the current in inductor IL.
In TM operation, operation is never exactly done at the borderline between DCM and CCM but slightly in DCM. In fact, the transistor M is not turned or conveniently when the current of the inductor is zeroed, as the voltage Vds in that moment is still equal to the output voltage Vout (typically 400 V). Therefore, the parasitic capacitance Cd associated with the drain terminal in that moment has energy equal to ½·Cd·Vout2 which would be dissipated in the resistance RDS(on) of transistor M when it is turned on. If instead the turn-on is delayed until the oscillation of voltage Vds resulting from zeroing the current IL of the inductor reaches its minimum, equal to 2Vin−Vout, the power stored in the parasitic capacitance Cd and dissipated in the transistor M at the turning-on would be considerably reduced.
Moreover, if 2Vin−Vout<0 (i.e., Vin<Vout/2), where the body diode of transistor M substantially cuts the oscillation to zero, these energy losses would be zeroed resulting in the so-called “soft-switching”. In part due to their operation and in part due to the introduction of intentional delays, zero current detection circuits or ZCD inside the controllers PFC, such as that shown in FIG. 1, allow the transistor M to be turned on at the drain oscillation valley (“valley switching”); this delay is indicated by Td, which is equal to half the period of said oscillation. This slightly moves the operation in DCM, but the remarks made on the pure TM are still valid, at least until Td is negligible with respect to the switching period, which typically occurs in a fairly large field of operating conditions of the converter if values Vin>>0 are considered, which are the significant ones in terms of the power transfer.
During the oscillation of voltage Vds, the current IL of inductor L becomes negative by passing through the parasitic capacitance of transistor M and, also possibly the body of transistor M if the voltage Vds reaches zero and, thus, directly biases it.
In this latter case, shown in the left-hand time diagrams, the voltage Vds reaches zero after a time Td1<Td. Until that moment, the current IL of the inductor is sinusoidal, but from that moment on, due to the turning on of the body diode which sets a voltage substantially equal to Vin at its terminals, it starts linearly increasing and at the instant Td is still negative. At this point, the transistor M (the voltage Vgs is forced high) is turned on and the direct current ramp starts. The current becomes positive at the instant Td2>Td. Therefore, there is a time interval in which transistor M is turned on, but the current IL of the inductor is negative. It should be noted that, if the input voltage is such that the peak voltage Vpk is Vpk<Vout/2 (which occurs with the American or Japanese power line, for example), this time interval exists in the entire power line cycle. The ratio of the duration of this interval to that of the switching cycle becomes increasingly greater as the voltage Vin decreases, thus reaching the maximum at the zeroes of the supply voltage (Vin=0). In addition to this, as the current peak tends to zero when Vin tends to zero, the negative peak of the inductor current may even become higher than the positive peak around the zeros of the supply voltage.
If 2Vin−Vout>0 (i.e., Vin>Vout/2), the oscillation valley of the voltage Vds remains at a positive value and the body diode is not turned on. Therefore, the negative portion of the current of the inductor is entirely a sinusoidal arch and the current is zero at the instant Td when transistor M is turned on (i.e., Td2=Td). Therefore, the time interval when the current is negative with the transistor M turned on is absent, but the negative peak of the inductor current (in this case of lower amplitude because the oscillation of voltage Vds is of lower amplitude) may be comparable to the positive peak around the zeroes of the supply voltage.
The current IL of the inductor linearly rises with a slope of
            ⅆ              I        L                    ⅆ      t        =      Vin    L  in each turn-on cycle of transistor.
Since the input voltage is sinusoidal, Vin=Vpk sin θ where θ is the phase angle of the supply voltage, therefore:
                    ⅆ                  I          L                            ⅆ        t              ⁢          (      θ      )        =            Vpk      L        ⁢    sin    ⁢                  ⁢          θ      .      Considering the initial value IL0 of the inductor current when transistor M is turned on, the peak value of the current of the inductor will be:
                    I        Lpk            ⁡              (        θ        )              =                  I                  L          ⁢                                          ⁢          0                    +                        Vpk          L                ⁢                  Ton          ·          sin                ⁢                                  ⁢        θ              ,
IL0=0 if Vin>Vout/2 while, by neglecting the variation of current in the interval between Td/2 and Td1, if Vin<Vout/2, IL0 may be assumed to be equal to the negative peak ILvy (which occurs at the instant Td/2), which is equal to:
                    I                  L          ⁢                                          ⁢          0                    ≈              I        Lvy              =                            Vin          -          Vout                Zd            =                                    Vpk            ⁢                                                  ⁢            sin            ⁢                                                  ⁢            θ                    -          Vout                Zd              ,
where Zd is the characteristic impedance of the resonant circuit consisting of the inductor and the parasitic capacitance on the drain terminal. Therefore, considering the preceding equations:
            I      Lpk        ⁡          (      θ      )        =      {                                                      -                              Vout                Zd                                      +                          Vpk              ⁢                                                          ⁢              sin              ⁢                                                          ⁢                              θ                ⁡                                  (                                                            1                      Zd                                        +                                                                  1                        L                                            ⁢                      Ton                                                        )                                                                                                        Vpk              ⁢                                                          ⁢              sin              ⁢                                                          ⁢              θ                        <                          Vout              ⁢                              /                            ⁢              2                                                                                      Vpk              L                        ⁢                          Ton              ·              sin                        ⁢                                                  ⁢            θ                                                              Vpk              ⁢                                                          ⁢              sin              ⁢                                                          ⁢              θ                        ≥                          Vout              ⁢                              /                            ⁢              2                                          
Therefore with a constant period Ton, there is only a sinusoidal envelope of the peak current for instantaneous values of the supply voltage which are higher than Vout/2. There is a reduction of the peak value ILpk(θ) for values less than Vout/2 and, accordingly, a distortion of the envelope due to the constant term −Vout/Zd, which reduction is as great as said instantaneous voltage is low. It is obvious that said distortion results in the distortion of the mains current and therefore in a greater THD and a lower PF.
Furthermore, the reduction of the peak current has a further deleterious action on the THD: the increase of crossover distortion, seen as a brief flat zone in the waveform of the input current close to the zeroes of the supply voltage.
This distortion growing as the load of the PFC decreases and as the rms supply voltage increases, derives from the input-output energy transfer defect which occurs close to the zeros of the supply voltage. In that zone, the energy stored in the inductor—linked to the peak value of the current—is very low, insufficient to charge the parasitic capacitance Cd until reaching the voltage Vout (typically 400 V) so as to turn on the diode D and transfer the power of the inductor to the output. Therefore, the diode is not turned on over a certain number of switching cycles and the energy is partially returned to the filter capacitor arranged downstream the rectifier bridge. This is not discharged and keeps the bridge in inverse bias, by deleting the input current and performing a dead zone in the waveform of the line current.
The fact that the peak current for a given Ton is lower than the one expected in the region wherein Vin<Vout/2, results that the power transported around the zeroes of the supply voltage is further reduced with respect to the case of sinusoidal envelope. Thereby, the number of switching cycles is increased, in which there is no power transfer towards the output and, therefore, the dead zone of the current absorbed by the network widens, with the consequential increase of THD and further reduction of PF.
However the capacitor C1 of the boost converter in FIG. 1 absorbs a current given by:
      Ic    ⁢                  ⁢    1    =      C    ⁢                            ⅆ          Vin                          ⅆ          t                    .      Said current is a further distortion element; said current, added to the current absorbed by the converter, results in a greater distortion of the current absorbed by the power line.